Low Voltage SRAMs with Adequate Stability in Nanoscaled CMOS

Increased leakage current and device variability are the major challenges with CMOS technology scaling. Since Static Random Accessed Memory (SRAM) is often the largest component in the embedded digital systems or System-on-Chip (SoC), it is more vulnerable to those challenges. To effectively reduce SRAM leakage and/or active power, supply voltage (VDD) is often scaled down during standby and/or active operation. For ultra-low-energy applications, SRAM is even required to operate with VDD near/below the threshold voltage. However, SRAM stability are weakened under lower voltages. Furthermore, variation, especially mismatch, enormously degrades SRAM stability and yield. Our overall goal is to help designing low voltage SRAM for power/energy reduction while maintaining enough stability and yield in the presence of variations. We first investigate SRAM standby operation with VDD scaling, and propose a statistical method to fast and accurately predict the worst data retention voltage (DRV), i.e. the minimum VDD that an SRAM can preserve all the data during standby in the presence of variations. Then we propose an adaptive approach to achieve aggressive standby VDD scaling under process, voltage and temperature (PVT) variations. Our approach uses canary replica bitcells with online failure detectors and the feedback controller to an external DC-DC converter so that VDD can be adjusted with PVT changes tracked by canary replicas. Data reliability in aggressive VDD scaling is ensured by a critical failure threshold, which can be programmed for trading off leakage power savings with yield. Silicon results from both 90nm and 45nm test chips will be evaluated. We also propose several techniques to enhance the adaptiveness and automation of the canary system, and thoroughly analyze its effectiveness with considering of overhead sources as well as the technology scaling effect. After that, we will further investigate SRAM yield under lower voltages. With technology scaling, SRAM yield loss due to degraded stability limits the lowering of the minimum VDD in dynamic voltage-and-frequency scaling (DVFS) systems or ultra-low-energy systems. Accurate yield analysis becomes indispensable. Therefore, we propose to estimate yield with accurate and fast analysis of the failure probability under variations for lower supply voltages.